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Winbond Host Interface SD/SDIO/MMC Memory Card Bridge W86L488
Preliminary W86L488
W86L488 Data Sheet Revision History
Pages 1 2 P6, P8, P10, P11, P24, P25, P26, P41, P42, P43, P44, P45, P46 Dates Aug. 2002 Dec. 2002 Version 0.50 0.60 Version on Web Main Contents First published. Add QFN package. 1. Modify pin function of CLK, ACLK, BCLK, XASN, XDRQN, 0.70 2. Revised function description of Data Access Request & Interrupt. 3. Revised Reference Schematic
3
May 21, 2003
4 5 6 7 8 9 10
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
Table of Contents1. 2. 3. GENERAL DESCRIPTION......................................................................................................... 1 FEATURES................................................................................................................................. 1 PIN CONFIGURATIONS ............................................................................................................ 2 3.1 3.2 4. W86L488Y Pin Configuration ............................................................................................ 2 W86L488AY Pin Configuration.......................................................................................... 3
PIN DESCRIPTIONS .................................................................................................................. 4 4.1 4.2 W86L488Y Pin Descriptions.............................................................................................. 4 W86L488AY Pin Descriptions ........................................................................................... 7
5.
BLOCK DIAGRAM ................................................................................................................... 11 5.1 5.2 W86L488Y Block Diagram .............................................................................................. 11 W86L488AY Block Diagram ............................................................................................ 12
6.
REGISTER ................................................................................................................................ 13 6.1 6.2 W86L488Y Register ........................................................................................................ 13 W86L488AY Register ...................................................................................................... 16
7.
FUCNTIONAL DESCRIPTION ................................................................................................. 19 7.1 7.2 7.3 7.4 Host Interface .................................................................................................................. 19 Card Inserting and Removing.......................................................................................... 24 Reset Action .................................................................................................................... 25 Clock Source ................................................................................................................... 25
8.
ELECTRICAL CHARACTERISTICS........................................................................................ 26 8.1 8.2 8.3 8.4 8.5 Absolute Maximum Ratings* ........................................................................................... 26 Recommended Operating Conditions ............................................................................. 26 Power Supply Characteristics.......................................................................................... 26 Digital Characteristics...................................................................................................... 27 Timing Characteristics ..................................................................................................... 27
9.
HOW TO READ THE TOP MARKING ..................................................................................... 33
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
10.
PACKAGE DIMENSIONS ........................................................................................................ 34 10.1 10.2 W86L488Y Package Dimensions ................................................................................ 34 10.2 W86L488AY Package Dimensions...................................................................... 35
11.
REFERENCE SCHEMATIC ..................................................................................................... 36 11.1 11.2 W86L488Y Reference Schematic................................................................................ 36 W86L488AY Reference Schematic ............................................................................. 39
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Preliminary W86L488
1. GENERAL DESCRIPTION
The W86L488 is a SD/SDIO/MMC interface bridge between microprocessor and SD/SDIO/MMC device. The data width of microprocessor is 8 or 16-bits. W86L488 supports synchronous or asynchronous type of host interface. It also supports DMA and Interrupt type of transfer mode to improve data transfer performance. The signals on the SD bus are captured or driven by W86L488. W86L488 is monitored and controlled by microprocessor via internal registers. W86L488 fits for most of IA devices, such as PDA, Cellular Phone, DSC, and MP3 player.
2. FEATURES
* * * * * * * * * * * * * * * Compliant with SD spec. Version 1.01. (Support SDIO) Compliant with MMC spec. Version 3.2. Simultaneously access two ports of SD/SDIO/MMC supported. (W86L488AY only) Support physical layer commands of SD/SDIO/MMC interface. Support SD/MMC and SPI mode for SD/SDIO/MMC interface. Support Keitaide-Music MMC card commands in SPI mode. Support SDIO interrupt and bus suspend/resume operation. Built-in 128 bytes data buffer for data transmit (send/receive). Support two types of Host microprocessor Interface access - synchronous and asynchronous. DMA and Interrupt transfer mode supported. Host microprocessor Interface support (Such as: Motorola's Dragon Ball series;Intel's Strong ARM, ARM series; Hitachi's SH2 series; Fujisui's FR30) Support 8/16 bits data bus of Microprocessor I/F. Built-in 3.58 to 25MHz crystal driver circuit, support external oscillator or crystal clock. Operation voltage: 2.7~3.6V for SD/SDIO/MMC, 2.5/3.3V for Host CPU interface. 48/64-pin QFN package.
Ordering Information
Part Number W86L488Y W86L488AY Description 1Port SD/SDIO 2Port SD/SDIO Package Type 48-PIN QFN 64-PIN QFN Production Flow Commercial, 0oC to +70oC Commercial, 0oC to +70oC
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
3. PIN CONFIGURATIONS
3.1 W86L488Y Pin Configuration
XDAKN/XASN
XCSN
XRDN/XRWN
XDRQN/XRDYN
XWRHN/XBE0
XWRLN/XBE1
HCKI
GIO0
GIO1
26
36
35
34
33
32
VSS
A3
31
30
29
28
27
A2 A1 XTYP2 D15/A0 D14 VSS VDDH D13 D12 D11 D10 D9
37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11
GIO2
25 24 23 22 21 20 19 18 17 16 15 14 13 12
GIO3 GIO4 DAT1/IRQ DAT0/CDO CLK VDD3 VSS CMD/CDI DAT3/CS DAT2 XTO XTI
XINTN
D6
VSS
D8
D7
D5
D4
D3
D2
D1
D0
Fig. 3-1 W86L488Y Pin Assignment (48-pin QFN).
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RSTN
Preliminary W86L488
3.2 W86L488AY Pin Configuration
XDRQN/XRDYN HCKI GIO6
XWRLN/XBE1 XWRHN/XBE0 XRDN/XRWN
VSS XDAKN/XASN
GIO5 XCSN
A2 A1 GIO7 XTYP2 GIO8 D15/A0 D14 VSS TEST VDDH GIO9 D13 D12 D11 D10 D9
49 50 51 52 53 54 55 56 57 58 59 60 50 61 62 63 64
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 2 3 4 5 6 7 8 9 17 10 11 12 13 14 15 16
GIO0 GIO1 GIO2
GIO3
A3
A4
GIO4 BDAT1/BIRQ BDAT0/BCDO BCLK ADAT1/AIRQ ADAT0/ACDO ACLK VDD3 VSS ACMD/ACDI ADAT3/ACS ADAT2 BCMD/BCDI BDAT3/BCS BDAT2 XTO
D8
D7
D6 D5
D4
GIO11 VSS D3
GIO10
D2 D1 D0
XINTN RSTN
Fig. 3-2 W86L488AY Pin Assignment (64-pin QFN).
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Publication Release Date: May 21, 2003 Revision 0.70
XTI
Preliminary W86L488
4. PIN DESCRIPTIONS
4.1
Pin 21
W86L488Y Pin Descriptions
Name DAT0/CDO Type DO/DI SD/MMC mode: Data line bit 0 signal for SD/SDIO card, data signal for MMC card. SPI mode: Card data output in SPI mode. Description
SD/SDIO/MMC Interface (VDD3 powered):
22
DAT1/IRQ
DO/DI
SD/MMC mode: Data line bit 1 signal for SD/SDIO card or interrupt request for SDIO. SPI mode: No use.
15
DAT2
DO/DI
SD/MMC mode: Data line bit 2 signal for SD/SDIO card or read wait for SDIO. SPI mode: No use.
16
DAT3/CS
DO/DI
SD/MMC mode: Data line bit 3 or Card detect for SD/SDIO card. SPI mode: Card select.
17
CMD/CDI
DO/DI
SD/MMC mode: Command response for SD/SDIO card or MMC card. SPI mode: Card data input. This pin will tri-state when the command is not driven.
20
CLK
DO
Clock output signal for SD/SDIO card or MMC card. This pin will stay at high or low when card clock is not needed depends on the state of CKDH bit setting.
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Preliminary W86L488
4.1 W86L488Y Pin Descriptions, continued
Pin 13 14 28 35 36:38 40
Name XTI XTO HCKI XCSN A[3:1] D15/A0
Type DI DO DI DI DI DI/DO
Description Clock driver input signal, may be used as external clock input. Clock driver output signal. Host clock input. Chip select input pin, active low. Address input pins. Data bus D15 pin, D[15:8] is the high byte of the data bus, D15 also used as A0 when 8-bit CPU data size. In 8-bit mode, internal register high byte (D15:8) will accessed at data bus [7:0] when A0 = 1, low byte (D7:0) will accessed at data bus [7:0] when A0 = 0.
Crystal Driver (VDD3 powered):
Host Interface Signal (VDDH powered):
41 44:48 1:5 7:10 33
D14 D[13:9] D[8:4] D[3:0] XWRHN/ XBE0
DI/DO DI/DO DI/DO DI/DO DI
Data bus D14 pin. Data bus D[13:9] pins. Data bus D[8:4] pins, D[7:0] is the low byte of the data bus. Data bus D[3:0] pins. Type 1: High byte (D15 to D8) write control pin, active low. Type 2: High byte (D15 to D8) data valid pin, active low.
34
XWRLN/ XBE1
DI
Type 1: Low byte (D7 to D0) write control pin, active low. Type 2: Low byte (D7 to D0) data valid pin, active low.
11
XINTN
DO
Interrupt request pin, active low.
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
4.1 W86L488Y Pin Descriptions, continued
Pin 32
Name XRDN/ XRWN
Type DI Type 1:
Description Read control pin, active low. Type 2: Read write control pin, 1: read 0: write
30
XASN
DI
Type 1: None. Type 2: Bus access cycle start pin, active low.
29
XDRQN/ XRDYN
DO
Type 1: Data Access request pin, active low. Type 2: Bus cycle complete pin, active low.
39
XTYP2
DI
Host interface type 2 select pin, 0: type 1 mode. 1: type 2 mode.
General I/O Port Signal (VDD3 powered):: 27:23 GIO[0:4] DI/DO 5-bit general input output port signals. GIO0 pin can be used as dedicate card insert detect. Input and active low in default. Reset input, hardware reset input, active low.
Other Signal (VDDH powered): 12 RSTN DI
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Preliminary W86L488
4.1 W86L488Y Pin Descriptions, continued
Pin Power: 19 43 6,18, 31,42
Name VDD3 VDDH VSS x4
Type DP DP DP Power supply 3.3V.
Description
Power supply 2.5V or 3.3V for Host I/F. *1 Ground (4 pins).
Type: DP is Power, DI is Digital Input, DO is Digital Output. Note*1: When Host I/F voltage is 2.5V, VDDH connects to 2.5V. When Host I/F voltage is 3.3V, VDDH connects to 3.3V.
4.2
Pin 27 30
W86L488AY Pin Descriptions
Name ADAT0/ACDO BDAT0/BCDO Type DO/DI SD/MMC mode: Data line bit 0 signal for SD/SDIO card, data signal for MMC card. SPI mode: Card data output in SPI mode. Description
SD/SDIO/MMC Interface (VDD3 powered):
28 31
ADAT1/AIRQ BDAT1/BIRQ
DO/DI
SD/MMC mode: Data line bit 1 signal for SD/SDIO card or interrupt request for SDIO. SPI mode: No use.
21 18
ADAT2 BDAT2
DO/DI
SD/MMC mode: Data line bit 2 signal for SD/SDIO card or read wait for SDIO. SPI mode: No use.
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
4.2 W86L488AY Pin Descriptions, continued
Pin 22 19
Name ADAT3/ACS BDAT3/BCS
Type DO/DI SD/MMC mode:
Description Data line bit 3 or Card detect for SD/SDIO card. SPI mode: Card select.
23 20
ACMD/ACDI BCMD/BCDI
DO/DI
SD/MMC mode: Command response for SD/SDIO card or MMC card. SPI mode: Card data input. This pin will tri-state when the command is not driven.
26 29
ACLK BCLK
DO
Clock output signal for SD/SDIO card or MMC card. This pin will stay at high or low when card clock is not needed depends on the state of CKDH bit setting. Clock driver input signal, may be used as external clock input. Clock driver output signal. Host clock input. Chip select input pin, active low. Address input pins. Data bus D15 pin, D[15:8] is the high byte of the data bus, D15 also used as A0 when 8-bit CPU data size. In 8-bit mode, internal register high byte (D15:8) will accessed at data bus [7:0] when A0 = 1, low byte (D7:0) will accessed at data bus [7:0] when A0 = 0.
Crystal Driver (VDD3 powered): 16 17 38 45 47:50 54 XTI XTO HCKI XCSN A[4:1] D15/A0 DI DO DI DI DI DI/DO
Host Interface Signal (VDDH powered):
55 60:64 1:5 9:12
D14 D[13:9] D[8:4] D[3:0]
DI/DO DI/DO DI/DO DI/DO
Data bus D14 pin. Data bus D[13:9] pins. Data bus D[8:4] pins, D[7:0] is the low byte of the data bus. Data bus D[3:0] pins.
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Preliminary W86L488
4.2 W86L488AY Pin Descriptions, continued
Pin 43
Name XWRHN/ XBE0
Type DI Type 1:
Description High byte (D15 to D8) write control pin, active low. Type 2: High byte (D15 to D8) data valid pin, active low.
44
XWRLN/ XBE1
DI
Type 1: Low byte (D7 to D0) write control pin, active low. Type 2: Low byte (D7 to D0) data valid pin, active low.
42
XRDN/ XRWN
DI
Type 1: Read control pin, active low. Type 2: Read write control pin, 1: read 0: write
13 40
XINTN XASN
DO DI
Interrupt request pin,active low. Type 1:
None.
Type 2: Bus access cycle start pin, active low.
39
XDRQN/ XRDYN
DO
Type 1: Data Access request pin, active low. Type 2: Bus cycle complete pin, active low.
52
XTYP2
DI
Host interface type 2 select pin, 0: type 1 mode. 1: type 2 mode.
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
4.2 W86L488AY Pin Descriptions, continued
Pin 46, 32:36 7, 6, 59, 53, 51,37
Name GIO[5:0]
Type DI/DO
Description 6-bit general input output port signals of port A. GIO0 pin can be used as dedicate card insert detection of port A. Input and active low in default (GIO[4:0] powered by VDD3, GIO5 powered by VDDH). 6-bit general input output port signals of port B. GIO6 pin can be used as dedicate card insert detection of port B. Input, active low in default (GIO6 powered by VDD3, GIO[11:7] powered by VDDH). Reset input, hardware-reset input, active low. Test input, must connected to VSS. Power supply 3.3V. Power supply 2.5V or 3.3V for Host I/F. *2 Ground (4 pins).
General I/O Port Signal:
GIO[11:6]
DI/DO
Other Signal (VDDH powered): 14 57 Power: 25 58 8, 24, 41, 56 Type: DP is Power, DI is Digital Input, DO is Digital Output. Note*2: When Host I/F voltage is 2.5V, VDDH connects to 2.5V. When Host I/F voltage is 3.3V, VDDH connects to 3.3V. VDD3 VDDH VSS x4 DP DP DP RSTN TEST DI DI
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Preliminary W86L488
5. BLOCK DIAGRAM
5.1 W86L488Y Block Diagram
HCKI
XTYP2
RSTN
VDD
VSS
XCSN A[3:1] XASN XRDYN XWRLN/XBE1 XWRHN/XBE0 XRDN/XRWN A0 D[15:0]/ D[7:0]
Address Decode Read /Write Controller
Host I/F Type Select
SD Bus Control
General Port Registers SD/SDIO/MMC Access Circuit
GIO[4:0]
Register File
17 Bytes Rsp Reg Serial to Parallel or Parallel to Serial Serial to Parallel or Parallel to Serial System clock Clock Divider
CLK
6 Bytes CMD Reg Data Packing Circuit 128 Bytes Data FIFO
Command Response Data Packing Circuit Crystal Driver
CMD
DAT[3:0]
XDRQN XDAKN XINTN
DMA Circuit
Interrupt Circuit
XTI
XTO
Fig. 5-1 Block Diagram of W86L488Y.
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
5.2 W86L488AY Block Diagram
HCKI
XTYP2
RSTN
VDDH
VDD3
VSS
XCSN A[4:1] XASN XRDYN XWRLN/XBE1 XWRHN/XBE0 XRDN/XRWN A0 D[15:0]/ D[7:0]
Address Decode
Host I/F Type Select
Global Sts & Ctrl Reg.
General Port Register
GIO[11:6] GIO[5:0]
Read /Write Controller
Register File
17 Bytes Rsp Reg 6 Bytes CMD Reg
SD Bus Control
SD/SDIO/MMC Access Circuit
BCLK ACLK
Data Packing Circuit
Serial to Parallel or Parallel to Serial Serial to Parallel or Parallel to Serial
Command Response Data Packing Circuit Crystal Driver
BCMD ACMD BDAT[3:0] ADAT[3:0]
128 Bytes Data FIFO
XDRQN XDAKN XINTN
DMA Circuit Interrupt Circuit
Clock Divider
XTI
XTO
Fig. 5-2 Block Diagram of W86L488AY.
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Preliminary W86L488
6. REGISTER
The registers in the W86L488Y/AY are direct access registers and indirect access registers. The direct access registers and indirect access registers are listed as follows:
6.1
Addr A[3:1]
W86L488Y Register
Register Name (note 1) Content (note 2)
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Direct Access Registers: 000 Command Pipe Reg. (WO) Response Reg. (RO) 001 001 Status Reg. (RO) Control Reg. (bit 8 WO, R/W) 010 010 011 011 Receive Data Buffer (R/O) Transmit Data Buffer (WO) Interrupt Status Reg. (RO) Interrupt Enable Reg. (R/W) General I/O Port Data Reg. (R/W) General I/O Port Control Reg. (R/W) General IP Interrupt Status Reg. (RC) General IP 0 X 0 0 X 0 0 X 0 0 X 0 0 X 0 0 X 0 0 X 0 Status 0 0 0 0 1 0 0 0 0 0 0 0 Control 0 0 0 0 1 Command pipe registers / Response registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Receive data buffer 0 X 0 0 GIO data 0 0 0 X X X X X 0 GIO interrupt status 0 0 0 0 0 0 0 0 GIO interrupt enable Publication Release Date: May 21, 2003 Revision 0.70 0 0 0 GIO control 0 0 0 0 0 Interrupt enable 0 0 0 1 1 0 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X Transmit data buffer Interrupt status
100
100
101
101
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Preliminary W86L488
Interrupt Enable Reg. (R/W) 110 111 Index Address Reg. (R/W) Index Data Register 0 X X X X X X X X X X 0 M_Fn 1 1 1 1 1 S_Fn 1 1 1 0 0 0
-
0
0
0
0
0
0
0
0
Index address 0 X 0 X 0 X 0 X 0 X 0 X 0 X -
Index data register
Indirect Access Registers: 0000 0000 0001 Extend Status Reg. (RO) Setting Reg. (R/W) SDIO Bus Function Reg. (RO) SDIO Bus Control Reg. (bit[7:6] RO,
R/W)
Extend status 0 0 0 0 0 -
Setting register 0 0 1 0 0 0 0 0 1 -
0001
SDIO bus control 0 0 0 0 0 0 0
0010
Master Data Format Register (R/W) Master Block Count Register (R/W) Slave Data Format Register (R/W) Slave Block Count Register (R/W) Nac Time-out Register (R/W) Error Status Reg. (RO) Buffer Service Length Register (RO) Ready & Data
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
Data length (master) 0 0 0 0 0 0 0 0
0 0 -
0011
Block count (master) 0 0 0 0 0 0 0 1
0
0
0100
Data length (slave) 0 0 0 0 0 0 0 0
0
0
-
0 0
0101
Block count (slave) 0 0 0 0 0 0 0 1
0
0
0110 0111
Nac time out register 0 0
Blv
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0 -
1 0 -
1 -
1 -
1 -
1 -
1 -
1 -
Error status
1000
Buffer service length 0 0 0 0 0 0 0 -
-
-
-
-
-
-
0 -
1000
F
-
-
-
-
-
-
d8
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Preliminary W86L488
Size Register (R/W) 1001 1010 Test Register (R/W) ID Code Register (RO) 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 Test register 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 ID Code register 0 0 0 0 0 0 0
Note 1:
R/W means the register can be read and write. RO means the register is read only. RC means the register is read only and read clear. WO means the register is write only.
Note 2: The data bit in the content is the initial value during hardware reset. 0: the bit value is 0. 1: the bit value is 1. X: the bit value is unknow. -: Undefined bit in the register and the value will read 0.
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
6.2
Addr A[4:1 ]
W86L488AY Register
Register Name (note 1)
Bit Bit Bit Bit Bit Bit
Content (note 2)
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Global Registers: 1000 1001 Global Status Reg. (RO) Global Control Reg. (bit[9:8] RO,R/W) Ready & Data Size Register (R/W) Command Pipe Reg. (WO) Response Reg. (RO) 0001 0001 Status Reg. (RO) Control Reg. (bit 8 WO, R/W) 0010 0010 0011 0011 0100 Receive Data Buffer (R/O) Transmit Data Buffer (WO) Interrupt Status Reg. (RO) Interrupt Enable Reg. (R/W) General I/O Port Data Reg. (R/W) General I/O Port Control Reg. (R/W) 0 X 0 0 X 0 0 X 0 0 X 0 0 X 0 0 X 0 0 X 0 Global status register 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d8 0 Global control register
1010
Direct Access Registers: 0000 Command pipe registers / Response registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Status 0 0 0 0 1 0 0 0 0
-
-
-
Control
-
-
-
-
1/1
0
0
0
0
0
0
1
Receive data buffer 0 X 0 0 GIO data 0 0 X X X X X X 0 0 0 0 GIO control 0 0 0 0 0 Interrupt enable 0 0 0 1 1 0 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X Transmit data buffer Interrupt status
0100
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Preliminary W86L488
0101 General IP Interrupt Status Reg. (RC) General IP Interrupt Enable Reg. (R/W) Index Address Reg. (R/W) Index Data Register GIO interrupt status 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X 0 M_Fn 1 1 1 1 1 S_Fn 1 1 1 0 0 0
-
-
-
-
-
-
-
-
-
0101
GIO interrupt enable 0 0 0 0 0 0 0
0110 0111
Index address 0 X 0 X 0 X 0 X 0 X 0 X 0 X -
Index data register
Indirect Access Registers: 0000 0000 0001 Extend Status Reg. (RO) Setting Reg. (R/W) SDIO Bus Function Reg. (RO) SDIO Bus Control Reg. (bit[7:6] RO,
R/W)
Extend status 0 0 0 0 0 -
Setting register 0 0 1 0 0 0 0 0 1 -
0001
SDIO bus control 0 0 0 0 0 0 0
0010
Master Data Format Register (R/W) Master Block Count Register (R/W) Slave Data Format Register (R/W) Slave Block Count Register (R/W) Nac Time-out Register (R/W) Error Status Reg. (RO)
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
Data length (master) 0 0 0 0 0 0 0 0
0 0 -
0011
Block count (master) 0 0 0 0 0 0 0 1
0
0
0100
Data length (slave) 0 0 0 0 0 0 0 0
0
0
-
0 0
0101
Block count (slave) 0 0 0 0 0 0 0 1
0
0
0110 0111
Nac time out register 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 Error status
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
1000 Buffer Service Length Register (RO) Ready & Data Size Register (RO) Test Register (R/W) ID Code Register (RO)
Blv
Buffer service length 0 0 0 0 0 0 0 -
-
-
-
-
-
-
-
-
0 -
1000
F 0
0
0
0
0
0
0
d8 0
1001 1010
Test register 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 ID Code register
Note 1:
R/W means the register can be read and write. RO means the register is read only. RC means the register is read only and read clear. WO means the register is write only.
Note 2:
The data bit in the content is the initial value during hardware reset. 0: the bit value is 0. 1: the bit value is 1. X: the bit value is unknow. -: Undefined bit in the register and the value will read 0.
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Preliminary W86L488
7. FUCNTIONAL DESCRIPTION
7.1 Host Interface
The Host interface type may be type 1 or type 2 and the data size of the data bus may be 16-bit or 8bit. Host Interface Type 1: The Host interface type 1 is selected when XTYP2 pin is low. Figure 7-1 shows the timing of 16-bit CPU read and write in type 1. Figure 7-2 is the timing of 16-bit CPU write high byte and write low byte. Figure 7-3 and 7-4 show the timing of CPU 8-bit data bus read and write in type 1.
A[3:1] D[15:0] XCSN XRDN XWRHN XWRLN
DO[15:0] DI[15:0]
Fig. 7-1 16-bit Read and Write Access in Host I/F Type 1.
A[3:1] D[15:0] XCSN XWRHN XWRLN
DI[15:8] DI[7:0]
Fig. 7-2 High Byte and Low Byte Write Access in Host I/F Type 1.
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
A[3:1] A0(D15) D[7:0] XCSN XRDN
Register bit [15:8] will be read. Register bit [7:0] will be read. DO[15:8] DO[7:0]
Fig. 7-3 CPU 8-bit Data Bus Read Access in Host I/F Type 1.
A[3:1] A0(D15) D[7:0] XCSN XWRLN
Register bit [15:8] will be write. Register bit [7:0] will be write. DI[15:8] DI[7:0]
Fig. 7-4 CPU 8-bit Data Bus Write Access in Host I/F Type 1.
- 20 -
Preliminary W86L488
Host Interface Type 2: The Host interface type 2 is selected when XTYP2 pin is high. The data size of the CPU data bus may be 16-bit or 8-bit and the access cycle may be in 3-cycle or 2-cycle. Figure 7-5 shows the timing of CPU read write in type 2 and the access cycle is 3-cycle access, figure 7-6 shows the timing of CPU read write in type 2 and the access cycle is 2-cycle access.
HCKI A[3:1] D[15:0] XCSN XASN XRDYN XRW N XBE[1:0]
Read cycle Write cycle DO[15:0] DI[15:0]
Fig. 7-5 Read and Write Timing in H ost I/F T ype 2, 3-Cycle A ccess.
HCKI A[3:1] D[15:0] XCSN XASN XRDYN XRWN XBE[1:0]
Read cycle Write cycle DO[15:0] DI[15:0]
Fig. 7-6 Read and Write Timing in Host I/F Type 2, 2-Cycle Access.
- 21 -
Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
Data Access Request: Data access request XDRQN is used to notify the Host that the Host should write data to the transmit data buffer or read data from the receive data buffer in data write to the card or data read from the card. The Data access request action also effective when Host interface type 2 is selected. During data transmit to the card, the XDRQN will active if the data write command has been transfer to the card and the transmit data buffer have not enough data to transmit to the card. The XDRQN will not active if the transmit data buffer have enough data to transmit to the card. The last byte of the data should placed at bit [15:8] if the data length is odd byte and CPU data size is 16-bit. During data receive from the card, the XDRQN will active if the data read command has been transfer to the card and the data have been received in the receive data buffer. The XDRQN will not active if the data read command has been executed completedly and the receive data buffer is read out. The last byte of the data is located at bit [7:0] if the data length is odd byte and CPU data size is 16-bit. There are two types of data access request waveform, one is single access mode and the other is burst access mode. Single access mode is configured if DABST = low, XDRQN will inactive after each access receive or transmit data buffer, the XDRQN will re-active after four clock later. Figure 7-7 shows the waveform of Host access receive data buffer in single access mode (DABST = low). Burst access mode is configured if DABST = high, XDRQN will hold at active state until the data has been transferred completedly. The Host can access receive or transmit data buffer with higher speed continuously and regardless of the system clock. Figure 7-8 is the waveform of Host access transmit data buffer in burst mode (DABST = high).
System Clock A[3:1] D[15:0] XCSN XRDN XDRQN
010 010
Fig. 7-7 Host Read Receive Data Buffer in Single Access Mode (DABST = low).
- 22 -
Preliminary W86L488
System_ Clock A[3:1] D[15:0] XCSN XWRHN XWRLN XDRQN
010 010 010
Fig. 7-8 Host Write Transmit Data Buffer in Burst Access Mode (DABST = high).
Interrupt: The XINTN pin is used to notify Host that something happens or error occurs. The INT bit of status register can be read and check repeatedly if the Host cannot accept XINTN pin. XINTN will active (low) at the falling edge of system clock if any bit in the interrupt register is high, XINTN pin will return to high when write high to the related bit of the interrupt status register except DRQ interrupt in, the XINTN pin will go low again at four system clock cycles later if any other interrupt event is still pending.
System_ Clock A[3:1] D[15:0] XCSN XRDN XWRHN XINTN
011 011 1xxxxxxxb 0x80XX
Fig. 7-9 Timing of Interrupt in.
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
System_ Clock A[3:1] D[15:0] XCSN XRDN XWRHN XINTN
011 011 1xx0xxxxb 0x90XX
Fig. 7-10 Timing of Interrupt in (XINTN pin goes to low again).
7.2
Card Inserting and Removing
There are two method for Host to detect SD/SDIO or MMC card inserting or removing through W86L488, the first method is detected by CD/DAT3 pin, the second method is a dedicate switch on the SD/MMC slot can be connected to the GIO0 pin and set GIO0 to input direction. These two methods can be performed even if the W86L488 is in power down state. Method 1, CD/DAT3 as card detection: The CD/DAT3 of SD bus can be used as card detection if no data transfer on the DAT3, if SIEN bit of the control register is low and CD_IE and INT_E on the interrupt enable register are all high, card inserting or removing will generate interrupt. Host must read the interrupt status register and re-check the card state by read the CD bit on the extend status register. This detection method will not effective when wide bus on the SD bus is transfer. MMC card may not support this detection method. Method 2, GIO0, GIP6 as card detection (inserting): Some SD/MMC slot support external switch for card existing detection, the switch will on when SD/SDIO or MMC card is exist. GIO0 and GIP6 with a pull high resister can be used as card detection of port A and port B. In port A the Host can disable the GOEN0 bit on the general I/O port control register and enable the GIT_EN0 bit on the general I/O port interrupt enable register and enable GIT_IE and INT_E bits on the interrupt enable register. SD or MMC card inserting or removing will change the switch state then change the state of GIO0 pin and then generate interrupt to the Host. Host may re-check the card state by read the GIN0 bit on the general I/O port data register. The card insert status of port A and port B also can be read in the global status and control register. Figure 7-10 shows the waveform of GIO0 and GIOx when card insert and remove if GIO0 as card insert and GIOx as write protect input.
- 24 -
Preliminary W86L488
Inserting
Card is exist (GIN0 read 1)
Removing
GIO0
GIOx
(no WP)
(GINx read 1)
GIOx
(WP)
(GINx read 0)
Fig. 7-10 Card Insert use GIO0 and Write Protect use GIOx.
7.3
Reset Action
Hardware Reset: Hardware reset is performed by setting RSTN pin to low state for at least 1uS. The CPU data size will set to 16-bit default, all the registers will set to default value. The receive and transmit data buffer will be cleared, all the internal logic will be reset to initial state. Software Reset: Software reset is executed by write the RST bit of the control register to 1, all the internal logic will be reset to initial state and receive and transmit data buffer will be cleared, but the content of registers are not affected. In W86L488AY, the port A and port B will reset at the same time if global software reset in the global control register is set. Data Buffer Reset: Data buffer reset is used to reset the receive data buffer and transmit data buffer simutaneously, the serial interface command will affected if the data receive or transmit command is progressing. Internal logic state and the content of registers are not affected.
7.4
Clock Source
The clock source of W86L488 is the waveform of XTO pin, if crystal is connected, the frequency may be from 3.58MHz to 25MHz, if the clock source is from external clock, XTI may be used as clock input and the maximum frequency is 25MHz. In W86L488AY, the clock driver will disabled when port A and port B are power down or global power down in the global control register is set.
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
8. ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings*
Parameter 1 Supply Voltage with respect to VVSS 2 Current at any pin other than supplies 3 Storage Temperature * Exceeding these values may cause permanent damage. Tst Symbol VVDD Rating -0.3 to 6 0 to 10 -65 to 150 Units V mA C
8.2
Recommended Operating Conditions
Characteristics Symbol VVDDH VVDD3 VVDD3 fXTL Top Rating 2.5 to 3.6 3.0 to 3.6 2.7to 3.0 25 0 to 70 Unit V V V MHz C
1 Host I/F Operation Voltage (referenced to VSS pin). 2 Operation Voltage (referenced to VSS pin). 3 Operation Voltage (referenced to VSS pin) (Note) 4 Clock Frequency at XTI pin 5 Operation Temperature
Note: Clock frequency not guaranteed up to 25MHz.
8.3
Power Supply Characteristics
Parameter Condition Power Supply (VVDD = 3.3V) Symbol Min Typ Max IQ IVDD IVDD (VVDD = 3.3V) IVDD IVDD 2 14 24 13 23 20 22 36 Units uA mA mA mA mA Test Test 1 Test 2 Test 2 Test 3 Test 3
(Measurement VDD3+ VDDH at VDD3 = VDDH)
1 Standby Supply Current 2 Operating Supply Current (Single port) Operating Supply Current (Single port)
3 Operating Supply Current (Dual port) 4
5 Operating Supply Current (Dual port)
: Typical figure are at VDIVDD = 3.3V and temperature = 25 C and are for design aid only, not guaranteed and not subject to production testing. Test 1: All input pins are VVDD or VVSS, configured as power down mode, output without loading and no clock input on the XTI and HCKI pins. Test 2: 25 MHz external clock input on the XTI pin, output without loading. Test 3: 25 MHz crystal connected at XTI and XTO pins, output without loading.
- 26 -
Preliminary W86L488
8.4 Digital Characteristics
Parameter 1 Output High Voltage 2 Output Low Voltage 3 Output High Voltage at SD4 output 4 Output Low Voltage at SD4 output 5 High Level Input Voltage 6 Low Level Input Voltage 7 Input Current 8 Input Capacitance Condition 2mA load 2mA sink 3mA load 3mA sink Symbol VOH VOL VOH VOL VIH VIL Iin Cin 10 0.7 0.3 1 0.9 0.1 Min. 0.9 0.1 Typ Max. Units VDD VDD VDD VDD VDD VDD uA pF Notes 1 1
: Typical figure are at VDVDD = 3.3V and temperature = 25C and are for design aid only, not guaranteed and not subject to production testing.
Note: All output pins except SD4 output.
8.5
Timing Characteristics
Parameter Symbol fXTI tXTIwh tXTIwl tXTIr tXTIf tXTOd fXTI fHCLK tHCLKwh tHCLKwl tHCLKI tHCLKf Min. 1 10 10 3.58 1 10 10 Typ. Max. 20 5 5 5 25 40 5 5 Units MHz nS nS nS nS nS MHz MHz nS nS nS nS Notes 1 1 1 1 1 2 3
Clock (figure 8-1) 1 XTI 2 XTI high pulse width 3 XTI low pulse width 4 XTI rise time 5 XTI fall time 6 XTO delay time 7 XTI crystal driver 8 HCLK frequency 9 HCLK high pulse width 10 HCLK low pulse width 11 HCLK rise time 12 HCLK fall time
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
8.5. Timing Characteristics, continued
Parameter Reset 1 RSTN Host Interface at Type 1 (figure 8-2, 8-3) 1 Access time 2 Address setup time 3 Address hold time 4 D[15:0] output delay time 5 D[15:0] output hold time 6 D[15:0] input setup time 7 D[15:0] input hold time 8 DMA request delay time 9 DMA request hold time Host Interface at Type 2 (figure 8-5) 1 Input signals setup time 2 Input signals hold time 3 Address setup time 4 Address hold time 5 XRDYN delay time 6 XRDYN hold time 7 D[15:0] output delay time 8 D[15:0] output hold time 9 D[15:0] input setup time 10 D[15:0] input hold time Interrupt (figure 8-4) 1 Interrupt delay time 2 Interrupt hold time
Symbol tRST tacc tAsu tAh tDod tDoh tDsu tDh tDRQd tDRQh tIF2su tIF2h tA2su tA2h tRDYd tRDYh tDod tDoh tDsu tDh tINTd TINTh
Min 4 100 10 5 10 10 5 5 10 5 10 5 5 10 10 5 5
Typ -
Max 30 20 20 20 30 20 20
Units cycle nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
Notes
4
5,6 5,7 8 9 2 2 10 10
2 2 5 5
- 28 -
Preliminary W86L488
8.5. Timing Characteristics, continued
Parameter 1 SD3 output delay 2 SD3 input setup time 3 SD3 input hold time 4 SD1,SD2,SD5,SD6 output delay time 5 SD1,SD2,SD5,SD6 input setup time 6 SD1,SD2,SD5,SD6 input hold time
Notes: 1. External clock input. 2. 20 pF output loading. 3. Crystal driver.
Symbol tSD3d tSD3Dsu tSD3h tSDnd* tSDnsu tSDnh
Min. 5 10 5 10 5
Typ. -
Max. 15 30 -
Units nS nS nS nS nS nS
Notes 2
Serial Interface Signals (figure 8-6, 8-7, 8-8, 8-9)
2
4. Minimum active pulse width of (XCSN and XRDN) or (XCSN and XWRHN and XWRLN). 5.: 40 pF output loading. 6. From the last active signal of XCSN or XRDN. 7. From the first in-active signal of XCSN or XRDN. 8. To the first in-active signal of XCSN, XWRHN or XWRLN, XWRHN or XWRLN related to the D[15:8] or D[7:0]. 9. From the first in-active signal of XCSN, XWRHN or XWRLN, XWRHN or XWRLN related to the D[15:8] or D[7:0]. 10. XCSN, XASN, XRWN and XBE[1:0] signals.
XTI
tXTOd
tXTIwh tXTIf
tXTIwl tXTIr
XTO
HCKI
tHCKIr
tHCKIwh tHCKIf
tHCKIwl
Fig. 8-1 Timing Characteristic of XTI, XTO and HCKI.
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Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
A[3:1]
tAsu tAh
DO[15:0] DI[15:0]
D[15:0]
tDod
tDoh
tDsu tDh
XCSN XRDN
tacc
XWRHN XWRLN
tacc
Fig. 8-2 Host Access Timing Characteristic in Host I/F Type 1.
XTO
tDRQd
XDRQN
tDRQh
Data_Acc (Note 1)
Fig. 8-3 Data Access Request Timing Characteristic.
XTO
tINTd
XINTN
tINTh
XRDN
Fig. 8-4 Interrupt Timing Characteristic.
Note 1: May be XRDN or XWRHN or XWRLN signals when DABST = low.
- 30 -
Preliminary W86L488
HCKI XCSN,XASN, XRWN,XBE[1:0]
tIF2su tIF2h
tA2su
tA2h
A[3:1]
tRDYd tRDYh
XRDYN
tDsu tDh
DI
tDod tDoh
DO
Fig. 8-5 Host Interface Type 2 Timing Characteristic.
CLK
tCMDd tCMDd
CMD
(output)
tCMDsu
tCMDh
CMD
(input)
Fig. 8-6 Serial Interface CMD Timing Characteristic (SD Mode).
- 31 -
Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
CLK
tDATd tDATd
DAT[3:0]
(output)
tDATsu tDATh
DAT[3:0]
(input)
Fig. 8-7 Serial Interface DAT[3:0] Timing Characteristic (SD M ode).
CLK
tCMDd tCMDd
CMD
(output)
tCMDh
tCMDsu
tCMDh
tCMDsu
CMD
(input)
Fig. 8-8 Serial Interface CMD Timing Characteristic (MMC Mode).
CLK
tDATd tDATd
DAT[3:0]
(output)
tDATsu tDATh
DAT[3:0]
(input)
Fig. 8-9 Serial Interface DAT[3:0] Timing Characteristic (MMC Mode).
- 32 -
Preliminary W86L488
9. HOW TO READ THE TOP MARKING
The top marking of W86L488Y
SMART@IO
W86L488Y
312AA01CSA
1st line: Winbond logo and SMART@IO Mark 2nd line: Part number of W86L488Y 3rd line: Tracking code A: 220 A A 01A SA 312: packages made in '03, week 12 assembly house ID; A means ASE, O means OSE, G means GR A: IC revision; A means version A, B means version B 01C: for internal use SA: for internal use
- 33 -
Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
10. PACKAGE DIMENSIONS
10.1 W86L488Y Package Dimensions
48- QFN
0.8
------------0.05 1
0.031 0 0.03
------------0.002 0.039
4.77
4.87
0.1878 0.1917
4.77 0.4 ---------
4.87 0.45 -----
0.1878 0.1917 0.0157 0.0178 ----0.0118
- 34 -
Preliminary W86L488
10.2 10.2 W86L488AY Package Dimensions
64- QFN
0.8
------------0.025 1
0.031 0 0.03
------------0.001 0.039
-----
6.85
-----
0.2697
----0.4 ---------
6.85 0.5 -----
-----
0.2697
0.0157 0.0197 ----0.0106
- 35 -
Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
11. REFERENCE SCHEMATIC
11.1 W86L488Y Reference Schematic
VCC3
C10 0.1u
D
C11 0.1u
D
VCC3 R62 RSTN XTYP2 12 39 13 14 28 11 35 32 34 33 29 30 15 16 17 20 21 22 27 26 25 24 23 RSTN XTI XTO HCKI XINTN NCS5 NOE NWE R65 0 XDRQN XDAKN DAT2 DAT3 CMD CLK DAT0 DAT1 INS GIO1 GIO2 GIO3 WP open R63 0
D
19 43 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A1 A2 A3 10 9 8 7 5 4 3 2 1 48 47 46 45 44 41 40 38 37 36 6 18 31 42
U2 VDD VDD
XTI D0 XTO D1 HCKI D2 D3 XINTN D4 XCSN D5 D6 XRDN/XRDWRN XWRLN/XBELN D7 D8 XWRHN/XBEHN D9 D10 XDRQN/XRDY XDAKN/XAS D11 D12 DAT2 D13 CD/DAT3 D14 D15/A0 CMD CLK A1 DAT0 A2 DAT1 A3 GIO0 GIO1 VSS GIO2 VSS GIO3 VSS GIO4 VSS W86L488D/48P_LQFP
D
- 36 -
Preliminary W86L488
VCC3
8 7 6 5
8 7 6 5
R15 R18 47K 47K R21 open
C7 0.1u
D
C8 10u
D
R17 47K 1 2 3 4 1 2 3 4
DAT2 DAT3 CMD CLK
R27 1 2 3 4 R28 1 2 3 4
22
D CON1
8 7 6 5
DAT0 DAT1 INS WP
22
8 7 6 5
9 1 2 3 4 5 6 7 8 10 11 12
D
DAT2 CD/DAT3 CMD VSS VDD CLK VSS DAT0 DAT1 INS WP CASE SD/MMC Card Scoket
XTO
R55
0
XTI
Q1 VCC3 20MHz R1 47K XDAKN HCKI GIO1 GIO2 GIO3 R2 47K R3 47K R4 47K R5 47K C13 30p C14 30p
D
D
- 37 -
Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
VCC3 VCC3
C4 22u
D
C5 1u
D
C6 0.1u
D
J1
A0 A2 A4
D0 D2 D4 D6 D8 D10 D12 D14
NWE NOE RSTN
XINTN
PXA255_XINT
2 4 C2 6 8 10 C4 12 14 16 18 20 22 24 C6 26 28 30 C8 32 34 36 38 40 42 44 C10 46 48 50 C12 52 54 56 58 60 62 64 C14 66 68 70 C16 72 74 76 78 80 82 84 C18 86 88 90 C20 92 94 96 98 100 102 104 C22 106 108 110 C24 112 114 116 118 120 122 124 C26 126 128 130 C28 132 134 136 138 140
C1 C2 C3 C4
C5 C6 C7 C8
C9 C10 C11 C12
C13 C14 C15 C16
C17 C18 C19 C20 C21 C22 C23 C24
C25 C26 C27 C28
1 3 C1 5 7 9 C3 11 13 15 17 19 21 23 C5 25 27 29 C7 31 33 35 37 39 41 43 C9 45 47 49 C11 51 53 55 57 59 61 63 C13 65 67 69 C15 71 73 75 77 79 81 83 C17 85 87 89 C19 91 93 95 97 99 101 103 C21 105 107 109 C23 111 113 115 117 119 121 123 C25 125 127 129 C27 131 133 135 137 139
A1 A3 A5
D1 D3 D5 D7 D9 D11 D13 D15
NCS5
D
AMP 536280-6
D
- 38 -
Preliminary W86L488
11.2 W86L488AY Reference Schematic
VCC3
C3 0.1u
D D
VCC3 D14 D15 GIO8 GIO7 A1 A2 R13 open R14 0
GIO9 D13 D12 D11 D10 D9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
D
D9 D10 D11 D12 D13 BGIO9 VDDH TEST VSS D14 D15/A0 BGIO8 XTYP2 BGIO7 A1 A2
D8 D7 D6 D5 D4 BWP GIO11 D3 D2 D1 D0 XINTN RSTN XTI
D
XTO BDAT2 BDAT3/BCS BCMD/BCDI ADAT2 ADAT3/ACS ACMD/ACDI VSS VDD3 ACLK ADAT0/ACDO ADAT1/AIRQ BCLK BDAT0/BCDO BDAT1/BIRQ AGIO4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D8 D7 D6 D5 D4 BGIO10 BGIO11 VSS D3 D2 D1 D0 XINTN RSTN NC XTI
A3 A4 AGIO5 XCSN XWRLN/XBE1 XWRHN/XBE0 XRDN/XRWN VSS XDAKN/XASN XDRQN/XRDYN HCKI BGIO6/CI_B AGIO0/CI_A AGIO1 AGIO2 AGIO3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
A3 A4 GIO5 NCS5 NWE NWEH NOE XDAKN XDRQN HCKI BINS AINS GIO1 GIO2 GIO3
R24
0
D
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 XTO BDAT2 BDAT3 BCMD ADAT2 ADAT3 ACMD VCC3 C9 0.1u
D D
W86L488D/64P_LQFP AWP BDAT1 BDAT0 BCLK ADAT1 ADAT0 ACLK
- 39 -
Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
VCC3
VCC3
R1 47K XDAKN HCKI GIO1 GIO2 GIO3 GIO5 GIO7 GIO8 GIO9 GIO11
R2 47K
R3 47K
R4 47K
R5 47K
R6 47K
R7 47K
R8 47K
R9 47K
R10 47K
JP1 1 2 HEADER 2
RSTN
R57 47k 1 C15 1u
D
D1 1N4148
SW1 2
VCC3
8 7 6 5
8 7 6 5
R15 R18 47K 47K R21 open
C7 0.1u
D
C8 10u
D
R17 47K 1 2 3 4 1 2 3 4
XTO
ADAT2 ADAT3 ACMD ACLK
R27 1 2 3 4 R28 1 2 3 4
22
D CON1
8 7 6 5
ADAT0 ADAT1 AINS AWP
22
8 7 6 5
9 1 2 3 4 5 6 7 8 10 11 12
D
DAT2 CD/DAT3 CMD VSS VDD CLK VSS DAT0 DAT1 INS WP CASE SD/MMC Card Scoket_A
XTI
Q1
20MHz C13 30p C14 30p
D
D
VCC3
8 7 6 5
8 7 6 5
R45 R47 47K 47K R48 open
C10 0.1u
D
C11 10u
D
R46 47K 1 2 3 4 1 2 3 4
BDAT2 BDAT3 BCMD BCLK
R49 1 2 3 4 R54 1 2 3 4
22
D CON2
8 7 6 5
BDAT0 BDAT1 BINS BWP
22
8 7 6 5
9 1 2 3 4 5 6 7 8 10 11 12
D
DAT2 CD/DAT3 CMD VSS VDD CLK VSS DAT0 DAT1 INS WP CASE SD/MMC Card Scoket_B
- 40 -
Preliminary W86L488
VCC3 VCC3
C4 22u
D
C5 1u
D
C6 0.1u
D
J1
A0 A2 A4
D0 D2 D4 D6 D8 D10 D12 D14
NWE NOE RSTN
XINTN
PXA255_XINT
2 4 C2 6 8 10 C4 12 14 16 18 20 22 24 C6 26 28 30 C8 32 34 36 38 40 42 44 C10 46 48 50 C12 52 54 56 58 60 62 64 C14 66 68 70 C16 72 74 76 78 80 82 84 C18 86 88 90 C20 92 94 96 98 100 102 104 C22 106 108 110 C24 112 114 116 118 120 122 124 C26 126 128 130 C28 132 134 136 138 140
C1 C2 C3 C4
C5 C6 C7 C8
C9 C10 C11 C12
C13 C14 C15 C16
C17 C18 C19 C20 C21 C22 C23 C24
C25 C26 C27 C28
1 3 C1 5 7 9 C3 11 13 15 17 19 21 23 C5 25 27 29 C7 31 33 35 37 39 41 43 C9 45 47 49 C11 51 53 55 57 59 61 63 C13 65 67 69 C15 71 73 75 77 79 81 83 C17 85 87 89 C19 91 93 95 97 99 101 103 C21 105 107 109 C23 111 113 115 117 119 121 123 C25 125 127 129 C27 131 133 135 137 139
A1 A3 A5
D1 D3 D5 D7 D9 D11 D13 D15
NCS5
D
AMP 536280-6
D
- 41 -
Publication Release Date: May 21, 2003 Revision 0.70
Preliminary W86L488
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Please note that all data and specifications are subject to change without notice. and companies mentioned in this data sheet belong to their respective owners.
All the trademarks of products
- 42 -

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